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1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view in 1 in 2 d 1 d 2 s 1 s 2 v? v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic dg611 top view s 1 s 2 v? v+ nc nc gnd v l s 4 s 3 lcc nc in 3 d 3 d 4 in 4 nc in 2 d 2 d 1 in 1 key 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dg611 dg611/612/613 vishay siliconix document number: 70057 s-00399?rev. g, 13-sep-99 www.vishay.com 1 high-speed, low-glitch d/cmos analog switches

fast switching? t on : 12 ns low charge injection: 2 pc wide bandwidth: 500 mhz 5-v cmos logic compatible low r ds(on) : 18 low quiescent power : 1.2 nw single supply operation improved data throughput minimal switching transients improved system performance easily interfaced low insertion loss minimal power consumption fast sample-and-holds synchronous demodulators pixel-rate video switching disk/tape drives dac deglitching switched capacitor filters gaas fet drivers satellite receivers

the dg611/612/613 feature high-speed low-capacitance lateral dmos switches. charge injection has been minimized to optimize performance in fast sample-and-hold applications. each switch conducts equally well in both directions when on and blocks up to 16 v p-p when off. capacitances have been minimized to ensure fast switching and low-glitch energy. to achieve such fast and clean switching performance, the dg611/612/613 are built on the vishay siliconix proprietary d/cmos process. this process combines n-channel dmos switching fets with low-power cmos control logic and drivers. an epitaxial layer prevents latchup. the dg611 and DG612 differ only in that they respond to opposite logic levels. the versatile dg613 has two normally open and two normally closed switches. it can be given various configurations, including four spst, two spdt, one dpdt. for additional information see applications note an207 (faxback number 70605).

four spst switches per package logic dg611 DG612 0 on off 1 off on logic ?0? 1 v logic ?1? 4 v
in 1 in 2 d 1 d 2 s 1 s 2 v ? v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view dg613 nc s 3 nc d 4 nc in 1 v l in 4 s 2 key s 4 in 3 d 1 top view d 3 v ? nc lcc in 2 v+ 9 gnd 10 11 12 13 4 d 2 5 6 7 8 1 2 3 19 20 14 15 16 17 18 s 1 dg613 dg611/612/613 vishay siliconix www.vishay.com 2 document number: 70057 s-00399 ? rev. g, 13-sep-99

four spst switches per package logic sw 1 , sw 4 sw 2 , sw 3 0 off on 1 on off logic ? 0 ? 1 v logic ? 1 ? 4 v

temp range package part number dg611/612 dg611dj 16-pin plastic dip DG612dj ? 40 to 85 c dg611dy 16-pin narrow soic DG612dy dg611ak/883, 5962-9325501mea 16-pin cerdip DG612ak/883, 5962-9325502mea ? 55 to 125 c dg611az/883, 5962-9325501m2a lcc-20 DG612az/883, 5962-9325502m2a dg613 16-pin plastic dip dg613dj ? 40 to 85 c 16-pin narrow soic dg613dy 16-pin cerdip dg613ak/883, 5962-9325503mea ? 55 to 125 c lcc-20 dg613az/883, 5962-9325503m2a

v+ to v ?? 0.3 v to 21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to gnd ? 0.3 v to 21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ? to gnd ? 19 v to 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v l to gnd ? 1 v to (v+) + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first v in a (v ? ) ? 1 v to (v+) + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first v s , v d a (v ? ) ? 0.3 v to (v ? ) + 16 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first continuous current (any terminal) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . current, s or d (pulsed at 1 s, 10% duty cycle) 100 ma . . . . . . . . . . . . . storage temperature: cerdip ? 65 to 150 c . . . . . . . . . . . . . . . . . . . . . plastic ? 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . power dissipation (package)b 16-pin plastic dip c 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin narrow soic d 600 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin cerdip e 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-pin lcc e 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v ? will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/ c above 75 c d. derate 7.6 mw/ c above 75 c e. derate 12 mw/ c above 75 c
v+ 5 v to 21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ?? 10 v to 0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v l 4 v to v+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in 0 v to v l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v analog v ? to (v+) ? 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
dg611/612/613 vishay siliconix document number: 70057 s-00399 ? rev. g, 13-sep-99 www.vishay.com 3

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 3 v v l = 5 v, v in = 4 v, 1 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog v ? = ? 5 v, v+ = 12 v full ? 5 7 ? 5 7 v switch on-resistance r ds(on) room full 18 45 60 45 60 r ds(on) i s = ? 1 ma, v d = 0 v room 2 source off leakage i s(off) v s = 0 v, v d = 10 v room hot 0.001 ? 0.25 ? 20 0.25 20 ? 0.25 ? 20 0.25 20 drain off leakage current i d(off) v s = 10 v, v d = 0 v room hot 0.001 ? 0.25 ? 20 0.25 20 ? 0.25 ? 20 0.25 20 na switch on leakage current i d(on) v s = v d = 0 v room hot 0.001 ? 0.4 ? 40 0.4 40 ? 0.4 ? 40 0.4 40 digital control input voltage high v ih full 4 4 input voltage low v il full 1 1 v input current i in room hot 0.005 ? 1 ? 20 1 20 ? 1 ? 20 1 20 a input capacitance c in room 5 pf dynamic characteristics off state input capacitance c s(off) v s = 0 v room 3 off state output capacitance c d(off) v d = 0 v room 2 pf on state input capacitance c s(on) v s = v d = 0 v room 10 bandwidth bw r l = 50 room 500 mhz turn-on time e t on r l = 300 , c l = 3 pf, v s = 2 v room 12 25 25 turn-off time e t off r l = 300 , c l = 3 pf, v s = 2 v see test circuit, figure 2 room 8 20 20 turn-on time t on r l = 300 , c l = 75 pf room full 19 35 50 35 50 ns turn-off time t off v s = 2 v see test circuit, figure 2 room full 16 25 35 25 35 charge injection e q c l = 1 nf, v s = 0 v room 4 ch. injection change e, g q c l = 1 nf, v s 3 v room 3 4 4 pc off isolation e oirr r in = 50 , r l = 50 f = 5 mhz room 74 db crosstalk e x talk r in = 10 , r l = 50 , f = 5 mhz room 87 db power supplies positive supply curent i+ room full 0.005 1 5 1 5 negative supply current i ? room full ? 0.005 ? 1 ? 5 ? 1 ? 5 a ground current i gnd room full ? 0.005 ? 1 ? 5 ? 1 ? 5
dg611/612/613 vishay siliconix www.vishay.com 4 document number: 70057 s-00399 ? rev. g, 13-sep-99

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 3 v v l = 5 v, v in = 4 v, 1 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 0 7 0 7 v switch on-resistance r ds(on) i s = ? 1 ma, v d = 1 v room 25 60 60 dynamic characteristics turn-on time e t on r = 300 , c = 3 pf, v = 2 v room 15 30 30 turn-off time e t off r l = 300 , c l = 3 pf, v s = 2 v see test circuit, figure 2 room 10 25 25 ns notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. q = q at v s = 3 v ? q at v s = ? 3 v .
dg611/612/613 vishay siliconix document number: 70057 s-00399 ? rev. g, 13-sep-99 www.vishay.com 5

r ds(on) ? drain-source on-resistance ( ? 4 ? 2 0 2 4 6 8 10 12 ? 5 400 350 300 250 200 150 100 50 0 r ds(on) vs. v d and power supply voltages v d ? drain voltage (v) v+ = 5 v v ? = ? 5 v v+ = 12 v v ? = ? 5 v v+ = 15 v v ? = ? 3 v i s = ? 1 ma r ds(on) ? drain-source on-resistance ( ? 4 ? 2024681012 400 350 300 250 200 150 100 50 0 r ds(on) vs. v d and temperature v d ? drain voltage (v) 25 c v+ = 15 v v ? = ? 3 v i s = ? 1 ma 125 c ? 55 c ? 4 ? 20246810 3 2 1 0 ? 1 ? 2 ? 3 ? leakage current (pa) , i d v d or v s ? drain or source voltage (v) i s(off), i d(off) i d(on) v+ = 15 v v ? = ? 3 v leakage current vs. analog voltage i s ? 55 0 125 leakage currents vs. temperature temperature ( c) ? 25 25 50 75 100 10 na 0.1 pa 100 pa 10 pa 1 pa i s(off), i d(off) i d(on) 1 na ? leakage (a) i , i s(off) d(off) 0 5 10 15 6 5 4 3 2 1 0 input switching threshold vs. v l v l ? logic supply voltage (v) v+ = 15 v v ? = ? 3 v v th ? logic input voltage (v) 16 14 12 10 8 6 4 2 0 24 22 20 18 ? 55 ? 35 ? 15 5 25 45 65 85 105 125 v+ = 15 v v ? = ? 3 v r l = 300 c l = 10 pf switching times vs. temperature t on t off time (ns) temperature ( c) ) )
dg611/612/613 vishay siliconix www.vishay.com 6 document number: 70057 s-00399 ? rev. g, 13-sep-99

charge (pc) v analog ? analog voltage (v) 20 10 0 ? 10 ? 20 ? 3 ? 2 ? 1012345678910 charge injection vs. analog voltage qd qs v+ = 15 v v ? = ? 3 v 1 10 100 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 f ? frequency (mhz) crosstalk and off isolation vs. frequency v+ = 15 v v ? = ? 3 v (db) crosstalk off isolation insertion loss (db) 1 10 100 1000 ? 24 ? 20 ? 16 ? 12 ? 8 ? 4 0 f ? frequency (mhz) r l = 50 ?3 db bandwidth/insertion loss vs. frequency ? 3 db point supply current (ma) 6 5 4 3 2 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 1 k 100 k 100 k 1 m 10 m v+ = 15 v v ? = ? 3 v v l = 5 v c x = 0, 5 v supply currents vs. switching frequency f ? frequency (hz) i+ i l i ?

v l v+ v ? s d dmos switch level translator input logic in x figure 1. driver
dg611/612/613 vishay siliconix document number: 70057 s-00399 ? rev. g, 13-sep-99 www.vishay.com 7

s 1 d 2 s 2 v s 1 v, 4 v v o in 2 r g = 50 1 v, 4 v x talk isolation = 20 log v s v l v o v+ in 1 50 c = rf bypass r l d 1 ? 3 v gnd v ? nc c +15 v c +5 v c c l (includes fixture and stray capacitance) v l r l r l + r ds(on) v o = v s v o 2 v v+ v ? in v ? s gnd r l 300 d c l +15 v +5 v figure 2. switching time 50% 20% 90% t on t off logic input 0 v 5 v v s = 2 v 0 v switch output t r < 10 ns t f < 10 ns figure 3. charge injection c l 1 nf d r g v o v+ s v ? 5 v in v l v g ? 3 v gnd +15 v +5 v figure 4. crosstalk

high-speed sample-and-hold in a fast sample-and-hold application, the analog switch characteristics are critical. a fast switch reduces aperture uncertainty. a low charge injection eliminates offset (step) errors. a low leakage reduces droop errors. the clc111, a fast input buffer, helps to shorten acquisition and settling times. a low leakage, low dielectric absorption hold capacitor must be used. polycarbonate, polystyrene and polypropylene are good choices. the jfet output buffer reduces droop due to its low input bias current. (see figure 5.) pixel-rate switch windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the dg613. for this application the two video sources must be sync locked. the glitch-less analog switch eliminates halos. (see figure 6.) gaas fet drivers figure 7 illustrates a high-speed gaas fet driver. to turn the gaas fet on 0 v are applied to its gate via s 1 , whereas to turn it off, ? 8 v are applied via s 2 . this high-speed, low-power driver is especially suited for applications that require a large number of rf switches, such as phased array radars.
dg611/612/613 vishay siliconix www.vishay.com 8 document number: 70057 s-00399 ? rev. g, 13-sep-99

clc111 75 + ? lf356 1 / 4 dg611 5 v control analog input input buffer s in d output buffer 5 v output to a/d +5 v +12 v ? 5 v c hold 650 pf polystyrene figure 5. high-speed sample-and-hold + ? clc410 75 1 / 2 dg613 background d output buffer composite output +5 v +12 v ? 5 v 75 titles 5 v control 75 250 1 / 2 clc114 250 figure 6. a pixel-rate switch creates title overlays 1 / 2 dg613 d 1 +5 v ? 8 v d 2 s 1 s 2 in 1 in 2 gnd v ? gaas rf in rf out v l v+ figure 7. a high-speed gaas fet driver that saves power 5 v

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